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A lot - too many to count. There is no problem with waveform distortion (as there is with the V3 when powering it via the ac adapter) because the only load on the adapter is the 100 kΩ or so of the voltage divider chain. That represents approx. 100 μA of load, and the adapter is rated at 9 V, 6va, which means the maximum load current is 666 mA. Divide the first into the second and there's your answer! (Though after the first few dozen you'll need to recalibrate the voltage.)

[I must make it clear that we're talking about emonTx V2. You can only do the same with the V3 provided that the link is removed and the V3 is powered by an external 5 V supply. Otherwise, you must have one adapter for each emonTx V3.]

Thanks for that Robert, I was indeed only referring to emonTx v2's at the time. I am currently using 3 x v2's but I want to expand the number for testing purposes, so I am actually adding 3 arduino mini pro's to the mix, they have voltage regs built in and are not powered via the AC/AC adapter and the measurements they make serve no purpose beyond testing the software and communication timing etc.

I was intending adding an ac voltage divider to each but now I'm wondering if 1 voltage divider could serve all 3 ac adc's as they are all mounted on 1 vero board. I would also like to simulate the additional 9 ct inputs and I assume I might get away with just using 1 or more voltage dividers on the 5vdc rail to give the 9 ADC's between 0 and 1v or is that not the case ??

This is just to create a test rig to test I²C comms and develop the sketch I'm adapting for this purpose, I'm using MartinR's PLL as I'm familiar with it and it doesn't use external libs for comms and measurements (ie jeelib and emonlib) and I'm concerned about the impact of another interrupt (TWI) and the calculations being now being triggered by emonHub over I²C rather than just every 5secs by the sketches main loop()..

So far it has worked well with 3 Tx's but with the potential to get synchronized data from around 120 nodes, the testing does seem quite feeble at this stage :-)

Paul

"I was intending adding an ac voltage divider to each but now I'm wondering if 1 voltage divider could serve all 3 ac adc's as they are all mounted on 1 vero board."

I don't see why not. But one slight advantage of separate dividers - component tolerances should give you slightly different values for each, that would differentiate them. (Or you could deliberately make the dividers different for the same purpose.)

"I would also like to simulate the additional 9 ct inputs and I assume I might get away with just using 1 or more voltage dividers on the 5vdc rail to give the 9 ADC's between 0 and 1v or is that not the case ??"

Not the case. The software filter will take the dc component out and you'll be left with nothing. If you want real c.t. signals, you can link the 'test' ADC inputs to a real c.t. input pin, or you can use a separate transformer and voltage divider (adjustable?) to give you 0 - 1 V ac simulating 0 - 100 A (approx) of current, connected where the burden resistor would be, i.e. you replace ct + burden with a 0 - 1 V alternating voltage, biased to sit at 1/2 rail as before. Again, you might want to fiddle the voltage to give you different numbers for each.

[I put the note re the V3's in case someone reading it thought they could do the same - but they can't!]

EDIT:
I've just thought to check your sketch - I should have done that first! You could indeed feed a dc signal into the current input, because Martin only subtracts an offset before multiplying by V for power or squaring for Irms.

But it only needs to go one side of the offset (mid-rail, hopefully) voltage.

So for the CT circuits could I in fact just do away with the mid-rail and apply a DC voltage relative to vcc/2 ? ie a voltage divider of 2 equal value resistors would in theory simulate 0amps and something like a 5:1 ratio divider would give me almost full scale in which ever direction it's biased and the value simulated dependent on "Ical" in the sketch. 

I also need to offset the ratio's 5:3 for 5v rather than 3.3v so maybe a gnd connected variable resistor in series with a fixed resistor 2/5's 2/3rds the size (of the VR) to 5v rail and connect the ADC's to the VR's wiper would be better ? does that sound right ???

Good news about the AC/AC as if I'm stacking v2's to work on a single phase I can just omit the voltage divider, mid-point components and the AC connector on all but one v2 and use a stackable header for AIO2.

​Paul

EDIT: corrected the confusing ratio reference

What you suggest should be OK for current but of course it will always give you zero average real power with the maths that you have. Of course, that doesn't matter if all you need is a set of numbers to test the interface, you just lie and and use apparent power instead!

If you look at the maths in the sketch, all should become clear. The long-term average (i.e. the quiescent voltage on the input pin) is subtracted from the present sample to give newI. That is squared for rms - that's OK, but when you multiply by newV (obtained similarly) to get instantaneous power, that will average to zero because V is alternately positive and negative each half-cycle while newI is always one or the other.

So if you need real power, you need an alternating voltage as I wrote above: use a separate transformer and voltage divider (adjustable?) to give you 0 - 1 V ac (1.6 V rms max if you have 5 V rails) simulating 0 - 100 A (approx) of current, connected where the burden resistor would be, i.e. you replace ct + burden with a 0 - 1.6 V alternating voltage, biased to sit at 1/2 rail as before.

To be honest, if I were to need test data, I wouldn't bother with the current inputs front end. I'd feed all current inputs with the voltage signal so as to give the ADC something to do, I'd run the maths to give a representative loading on the processor, and simply fudge the numbers it transmitted to give recognizable values to test the interface.

"that will average to zero because V is alternately positive and negative each half-cycle while newI is always one or the other"

I hadn't considered the lop sided averaging, not that it's really much of a concern

"I'd feed all current inputs with the voltage signal so as to give the ADC something to do,"

if I could just link all the ADC's together to load the calculations I would be happy, I have no need for the results, we know the calculations work and as long as all the devices are loaded and working, I have proper emontx's I can put anywhere in the chain to test actual measured results.

I currently report the interval since last poll in mSecs and the time taken for calcVIPF() to complete in uSecs plus an accumulating "energy" value calculated from the interval timer and a fixed "power" value, so the calculated results are being over written anyway.

"if I could just link all the ADC's together to load the calculations I would be happy"
You can be happy then! Here's what to do:

1 voltage front end,
all the processors have the same supply bus (0 V & 5 V rails)
link all the ADC inputs together

I don't see any harm there, nor any side effects (none that matter anyway).

Cheers Robert, this is good news, I haven't had a chance to try it yet but I hope to very soon.

Paul