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Basically - yes. The loop has to apply the high pass filter, the phasecal algorithm and accumulate the squared values of voltage and current for the rms calculations and the power for the real power average. If you look at the filter,
        filteredV = 0.996*(lastFilteredV+(sampleV-lastSampleV));
you might think that the brackets around "(sampleV-lastSampleV)" are redundant, but in fact they force the subtraction to be done first and that happens in fixed point arithmetic, then the rest of the calculation is done in floating point. Those brackets mean an integer subtraction instead of a floating point one and one less conversion to a float, and hence another two or three sample pairs per cycle.

The loop can be speeded up if you perform the calculations using fixed point arithmetic rather than floating point, but the fixed point calculations are a lot harder to understand and follow through.

When the ADC is free-running, my Mk2i PV Router code does approx 96 pairs of V & I samples per mains cycle.  The quoted period for a single conversion is 104 us, so that value looks spot on.  By use of integer maths, the main processor is only around 70% occupied.

Ok thanks for your answers Robert and Calypso. I was actually trying to solve a sub-problem in my 3-phase measurement sketch. Robert made the point that if you want to shift voltage phase by X degrees, you need to know how many samples in a cycle you have, and probably interpolate between 2 samples.

My idea was, if I know the # of samples in a cycle programmatically, I can do a dynamic calculation and determine between which 2 samples to interpolate.

But what I take from this discussion is:

1) I can't tell the number of samples from the code itself. But could by empirical measure when the system is running.

2) The number shouldn't change very much across iterations, but I suspect if I want to make this really stable I should avoid IF statements so that the code is more deterministic.

Does this make sense?

What you have to remember is, unless you have a highly reactive load and a correspondingly poor power factor, the actual phase shift you apply is not all that critical, because the curve is flat-topped. So a slight phase shift will have only a small effect on the real power value that you calculate.

Why are you worrying about IF statements? What branches are there in the main body of the main loop - while it is reading the 10 cycles and getting the numbers on which to base the calculations? I can't see any.

The other variables that you might not have thought about are the variation of mains frequency (1% is allowed either side of the nominal for us in the UK), and clock drift in your crystal. Both will affect the timing and hence introduce what looks like a phase error. And you can do nothing about that. Unless...

If you really want to avoid the problem altogether, you should be looking at MartinR's PLL sketch, adjust it so that it locks to 3n samples per cycle (say 48) and then (if phase 1 is the 0th) the second and third phases of a 4-wire system will be EXACTLY the 16th and 32nd samples in the array, and for your 2-phase 3-wire system the second phase will be the 8th sample; and they will stay there even if the frequency changes.
[For anyone who does not know the history, Amaury has a 3-wire 3-phase system, 230 V L-L and no neutral wire; and the loads are connected in delta. He is measuring two phases with respect to the third, so he has in effect a 2-phase system with 60° between the phases.]

There are a number of users of the sketch (on 4-wire) and they seem to have had no problem with setting it up empirically by following the instructions in the comments.