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Thanks for this insight.  Very interesting.

In my view, (shared by many others, I believe), there should be a 2.5V rail stabilized by an op-amp, and buffer op-amps on most or all of the ADC inputs.  Mine is modified in this way.

Hi, from another Robin,

Yes, that is a very interesting observation.  I've been seeing similar effects myself today when measuring V and I streams using a shared reference which is buffered.

My interest has been to determine the DC-offset of the system.  With a shared reference, there can only be one DC-offset.  Right?  Well, not necessarily it seems.  Using a LP filter, my voltage stream shows a constant DC offset of around 507.  By use of a second LP filter, my current sensor can show around a 7-level difference.  The resulting value from this LP filter is dependent on the direction and magnitude of the current, and is entirely repeatable. 

I don't have individual buffers on the V and I streams, only on the reference rail.

Do you have a decoupling capacitor connected to the bias chain midpoint? How does that affect it? Conventional wisdom says that when connecting a charged capacitor to another, the charges will be shared by the two series capacitors and the voltages will change in the inverse ratio of the capacitance.

Martin,

very good test with astonishing result. I can only backup your findings with my (subjective) experience. Since decreasing the voltage divider resistor values to 2 x 4k7 I get much more accurate readings especially at low current/power values. This was a long time ago, so I cannot give exact results, sorry. And I only have one emonTx hardware, so I cannot compare directly.

I understand that the use of 470k comes from the wish to get the supply current in sleep mode as low as possible and make battery operation possible. Are you using the original emonTx hardware for your tests?

Yes, original tx hardware. I take the point about battery operation but this is only really an issue when there's an a/c voltage input and I would expect that most people would use mains power in that case.

I can see how using a single reference would make things worse. You may have a low impedance reference but you also have a direct path between current and voltage inputs. Any ripple that the (relatively) large voltage input puts onto the reference will directly affect the current measurement. This is probably what Robin (calypso_rae) is seeing. It would be interesting to feed the reference voltage into another analogue input and try and plot the ripple. You could then experiment with capacitors on the reference voltage to see if you could improve the situation. Probably best to try good quality tantalum capacitors.

Any ripple that the (relatively) large voltage input puts onto the reference will directly affect the current measurement. This is probably what Robin (calypso_rae) is seeing. It would be interesting to feed the reference voltage into another analogue input and try and plot the ripple. 

Yes, Martin, that's just what I've been doing.  Adding an extra analogue measurement of the reference does not seem to affect the result of the current measurement which follows immediately.  So the ability of the ADC to measure a relatively small voltage immediately after measuring a much larger one does seem to be OK. 

With a modified version of my RawSamplesTool, I can now measure voltage, current and the reference voltage during one particular mains cycle.  These values are all written to arrays for subsequent analysis.  As far as I can see, changing the current has minimal effect on my measurements of the reference voltage.  What I have noticed, however, is that my measurements of the reference voltage do contain a few rogue values.  These values are generally 511 or 512, but during most recorded cycles I've seen the occasional 504 or 519.   I've no idea why these odd values might be occurring.

When just measuring V and I, I'm seeing around 67 loops per (50Hz) mains cycle.  With the additional measurement of Vref, that number drops to around 48.

Here is a spreadsheet with results for my triple-measurement tool in 3 conditions: first with no power at the CT, and then with 3kW in each direction (by reversing the CT). 

This is the graph for when no current is flowing.  I can't see any 50Hz ripple on my bufferered reference voltage, only the odd rogue value.

the rogue values do seem strange, maybe there's some fast noise spikes that you just catch occasionally?

If you want to increase the number of samples per cycle try this in your setup...

ADCSRA &= 0xf8; 
ADCSRA |= 0x06;

it doubles the ADC clock speed to 250kHz but seems to have no noticeable effect on the results. The ATMega328 data sheet says max 200kHz for full resolution but this document http://www.atmel.com/Images/doc2559.pdf implies it's ok to exceed that with the statement:"For optimum performance, the ADC clock should not exceed 200 kHz. However, frequencies up to 1 MHz do not reduce the ADC resolution significantly."

Thanks Martin, so far I've done nothing adventurous when taking analogue measurements.  The basic arrangement has always seemed fine to me.

The sketch that I've recently used for capturing raw data is attached.

Has anyone tried using the LM285LP-2.5 micropower voltage reference in place of one of the resistors of the potential divider?

(I'm still not at a point where I can easily try it before suggesting it.  They are 56p at Farnell.)

Changing the resistors isn't the solution!

When you stop to analyse what is going on, it is apparent that the switches in the multiplexer are working as a charge pump, transferring 14 pF (that is the value of the sample & hold capacitor) worth of charge from one input to the next each time they are switched.  With the bias supply decoupling capacitor at 10 µF, and assuming the current input is steady at 1.65 V and the voltage input is steady at 3.3 V, then the voltage on the current input decoupling capacitor will rise by about 2.4 µV on each reading - irrespective of the resistor values!  - until a new steady-state is reached.  What reducing the resistor values does is by shortening the time constant, allows that charge to drain away into the bias chain more quickly.

So the solution is a little more complicated - the decoupling capacitor should be increased - probably as far as the pcb layout will allow, but at the same time the resistor values should be reduced to maintain a sensible time constant so that the input settles sufficiently quickly at power-on.

There is an unfortunate side effect if that is done - it will allow overcurrent in the internal protection diodes of the analogue input, so a series resistor will be required to limit the input current and prevent damage to the processor chip.

[Note: For simplicity, I've ignored the minor complication that the voltage input is a.c. - of course what this means is it builds charge in one half cycle and drains it in the next, so a steady state is never reached. It superimposes a voltage ripple on the current wave, as demonstrated].

Sorry Robert, my Mac doesn't know how to open a Unix Executable File :(

? ? ?

No Unix executable files around here, your Mac is lying through its teeth. The file is an LTSpice circuit description - a simulation of two inputs and the sample & hold capacitor. As far as I know, LTSpice isn't available in a Mac version. But a version of Spice surely must be. The file is actually readable text describing the circuit that should be easy to convert to a different version.

Just for you....

And here's the current input crosstalk - in green (note the voltage input in blue for reference is divided by 50000)

As the amplitude of the crosstalk is small (0.01 LSB peak-peak) , it will only be significant if it causes the current input to cross into a different count when it otherwise would not have done.

Thanks Robert,

There may well be others who will appreciate the alternative format, rather than the .asc original

By way of verification that my buffered reference arrangement really does work without problems, here are the results from a simple test I've just run.  The test circuit was a standard Mk2 rig with the LM358 buffered reference.  To provide a direct measurement of the reference, the fixed end of the CT was fed to the Arduino's analogue i/p 0.

Measurements from all three inputs (reference, current, and voltage) were repeatedly taken and their min/max values noted.  During this process, the AC voltage was turned on and off a couple of times.  This caused the voltage data to change as expected, but the other two data streams were essentially unaffected.

In short, the buffered reference appears to be unaffected by the application of the AC voltage. 

Excellent analysis Robert (sorry for the delay in replying, I've been away from the computer for a few days)

To test the theory I tried putting a 1M potentiometer in parallel with one of the 3.3k resistors so that I could make very fine adjustments to the bias voltage. Sure enough, at certain voltages, there's a step change in the reported power of about 10W so as you predicted the lower value resistors don't solve the problem and I probably just hit a sweet spot with the particular resistor combination I used.

On the plus side it's pretty impressive that the system can resolve this level of power at all when you consider the range it can handle.

Robin's (Calypso_rae) buffer works in this situation because it presents a very low output impedance and the feedback action quickly sucks out the charge that has been dumped on its output. That isn't to say there might not be some narrow spikes of a microvolt or two while the feedback gets its act together.

(I presume you've read up on what happens with very low level inputs?)

I presume you've read up on what happens with very low level inputs?

No, I haven't but it sounds like I should :) I should probably go back and read a lot of useful stuff on here as I came into this pretty late.

....  I probably just hit a sweet spot with the particular resistor combination I used.

Must have been the same effect for me too. I clearly saw much better (lower) zero-power readings when changing to the lower resistance values. Thank you, Robert for making clear that this just occurred by chance and is not a 'real' effect.

Well, it is 'chance' that you hit it because it depends critically on the actual voltage as determined by resistor tolerances and drift and capacitor leakage and input bias currents and ... (etc, etc) and a 'real' effect because it is predictable if you know enough about those things and linearity in the ADC. The actual mechanism by which this happens is quite straightforward.  Trystan did some wonderful animated pages a few months ago demonstrating how the errors vary here, here and here, as well as this. You can recreate this with a low-valued pot in series with one of the bias resistors, or I did it with a pot across the supply with the wiper connected to the bias via a high value resistor, to 'pull' the bias about +/- 2 ADC steps.

So in the real world - chance.

But as I pointed out, reducing the resistor values changes the time constant, and you have to come down to 1 k to halve the ripple voltage (to 20 µV). Doubling the capacitor and halving the resistors does the same and leaves the settling time unchanged. But again as I pointed out, the input is then at risk because you have reduced the equivalent impedance in series with the input.

Interestingly, the charge pump effect disappears if the circuit is rearranged in the 'conventional' way, with the input transducers grounded at one end and the capacitor coupling the signal to the biassed input - as in a normal audio amplifier. All you see then are narrow spikes ( 2 mV high but only 200 ns wide according to my simulation) as the s&h capacitor discharges into the burden. I haven't tried to work out whether the ADC would see these or not.

There may be other factors at work, of course. I was only attempting to explain the mechanism of one input cross-talking into another via the sample & hold capacitor. I would expect common grounds and ground currents to have an effect too.

If I am following this correctly, would there be any mileage in making the ADC take a reference reading before each current measurement?

On emonTx for example, if a dummy plug was to be inserted in the spare current jack with terminating short to the bias network.....

Then you sample in the order:  voltage - reference - current,  voltage - reference - current,  etc....

I am thinking that this way the ADC sample and hold is always starting from the same point before taking that tricky current measurement.

Has this been thought of already?  Would it work? (I am still trying to catch up.)

There may be good reasons why it shouldn't or cannot be done?

I don't see how that will help. It adds to the cycle time

[Edit] and fudges rather than cures the problem.

It doesn't even do that when you think it through. It would just act as a charge pump on the spare input, then on the next reading transfer the voltage on that forward to the input it would have done it to in the first place. So it might alleviate the problem a little, but not cure it.

BTW, an 18 Ohm resister isn't a lot different to a short circuit when the charge on a 14 pF (yes, PICOFARAD) capacitor is being discussed, especially when compared with 235 kOhms!

Robp: would there be any mileage in making the ADC take a reference reading before each current measurement?

I'm so glad that someone else has suggested this.  I tried this very thing yesterday: V, ref, I, V, ref, I, ...

With that 3-way sequence, I saw a distinct reduction in the amount of calculated that is present per mains cycle.  I think this is because the new measurement sequence is effectively introducing a phase-shift between the V and I waveforms, so the Power Factor is no longer unity.  The V and I waveforms will only recombine correctly if their alternating samples are taken with even spacing.  This kind of effect is investigated in the set of graphs that I posted a couple of weeks ago on the PHASECAL thread.

I tried extending this idea to a 'balanced' 4-way sequence: V, ref, I, ref, calculations, V, ref, I, ref, calculations, ...   This resulted in a very strange effect.  I repeated the run and the strange effect appeared once more.  I was not actually using the Vref values, I was instead using a fixed value of 512 which appears to be correct for my rig.

(My reasons for trying out these new measurement sequences was somewhat different than is being discussed on this thread, but the results may be of interest)

A (slightly) interesting update on this. I tried removing the a/c input, and even the ADC voltage reading, and there's still a slight change of about 10W when the CT direction is changed. Made no sense to me for a while but I eventually concluded it must be due to 50Hz leakage in the system, possibly from the 5V supply (the setup was powered from a PC via USB).

Since the ADC mux leakage and this supply leakage must be adding to produce the 20W I was seeing it occurred to me that if I swapped the phase of the 9v a/c input they might cancel - so I tried it. Sure enough there is a significant reduction in the change in power when the CT direction is swapped, not enough to cancel though, there's still a few watts left. Probably of no practical use but I thought it was interesting.

I'm currently working on a version of Mk2 which uses a pair of HPFs rather than the LPF arrangement that I had before.  It will also have a 'tally' mode whereby per-cycle energy values can be 'tallied' for subsequent analysis.

Here is a 30s run for the 0W situation.  My CT is sitting on the floor around one core of an extension into which a couple of loads are connected, but not switched on.

Although there's quite a spread in the data, there's minimal long-term drift.  During that same measurement period, the energy bucket drifted by 16J, so that around 0.5W.

[Edit - in my post that follows this one, I meant to say 11 Joules of drift (over a 30-second period) rather than 11 Watts.  For some reason, I can't edit that post ...] [I have... RW]

Here is an equivalent run with the standard Mk2 fiter arrangement (LP + HP combo) .  This time there was only 11W 11 J of drift during the 30s measurement period. 

Hello everyone, well I'm starting here, and found that with resisencias of 470k cause problems to the input of the ADC, had not reviewed these comments but what I did is lower the resistance (100k) and apparently solucuinó but did not do a thorough analysis this.

Apparently this is not so, according to comments posted here
Finally. What is the most appropriate solution s must lower the value of the resistors?.

Because those resistors represent a large current drain when using batteries, the recommended value is 470 kΩ. If you are using mains power, then the value does not matter very much, but if you make it too small, the impedance of the loop formed by the resistors and decoupling capacitor in parallel and the input of the ADC may be low enough for a fault on the mains downstream of the c.t. to generate enough current to damage the protection diodes in the Atmel processor input circuit and cause it to fail.

Thanks, I think the 100k resistor I'm working with, is fine as it will not use batteries, and ye took some samples seem fine. I hope to continue working to get the final result.
Thank you, again.